1. Field of the Invention
The present invention relates to a filter device designed by charge domain operations (hereinafter, called a charge domain filter device).
2. Description of the Related Art
An SoC (system-on-chip) used in wireless communication, which is achieved by embedding an RF (radio frequency: high frequency) circuit and a digital circuit in a single CMOS (complementary metal oxide semiconductor) circuit chip, needs to allow the RF circuit to be provided as a compact unit and assure better energy efficiency in the RF circuit. In order to respond to these needs, the development of filtering and decimation technologies achieved through adoption of analog discrete-time signal processing technologies such as current mode sampling with a high-speed clock and switched capacitor circuits as disclosed in non-patent Reference Literature 1, is being actively pursued.
In addition, a charge domain filter circuit that includes only a transconductor and a switch to form a SINC filter circuit, the frequency characteristics of which assume SINC function characteristics without utilizing an operational amplifier, has been proposed as disclosed in Nonpatent Reference Literature 2 or Nonpatent Reference Literature 3. Since the filter in such a charge domain filter circuit is constituted with a transconductor and a switch alone, an RF signal in the GHz band can be directly sampled or filtered with the charge domain filter circuit. The following is a description of a charge domain filter circuit forming a SINC filter circuit.
FIG. 17 shows the structure adopted in a charge domain filter circuit forming a SINC filter circuit in the related art. As shown in FIG. 17, a charge domain filter circuit 10 forming a SINC filter circuit, proposed in the related art, includes a transconductor 12, a first switch 14, a second switch 16, a third switch 18, and capacitors 20a, 20b, 20c and 20d. 
FIG. 18 presents a timing chart of the clock signals applied to the charge domain filter circuit 10 shown in FIG. 17. Four clock signals Ø1, Ø2, Ø3 and Ø4 in FIG. 18, in different phases, are used to control the operations of the first switch 14, the second switch 16 and the third switch 18 in the charge domain filter circuit 10.
The transconductor 12 outputs a current in proportion to the voltage of an input signal.
A specific capacitor to be charged by applying the current output from the transconductor 12 is selected via the first switch 14. In the charge domain filter circuit 10 shown in FIG. 17, the first switch 14 is switched to a specific terminal based upon the four types of clock signals Ø1, Ø2, Ø3 and Ø4 and the capacitor corresponding to the selected terminal is charged.
A specific capacitor to be initialized by purging the residual charge is selected via the second switch 16. The second switch 16 is switched to a specific terminal based upon the four types of clock signals Ø1, Ø2, Ø3 and Ø4 in the charge domain filter circuit 10 in FIG. 17. The capacitor corresponding to the terminal selected at the second switch 16 is grounded and initialized by purging the residual electrical charge so as to purge the capacitor of any residual charge attributable to a previous signal.
A specific capacitor holding an electrical charge stored therein to be output to a circuit at a rear stage is selected via the third switch 18. The third switch 18 is switched to a specific terminal based upon the four types of clock signals Ø1, Ø2, Ø3 and Ø4 and as the specific terminal is selected, the electrical charge stored at the corresponding capacitor is output to the circuit at the rear stage in the charge domain filter circuit 10 shown in FIG. 17.
The terminals Ø1, Ø2, Ø3 and Ø4 at each of the switches, i.e., the first switch 14, the second switch 16 and the third switch 18, become connected when the corresponding clock signals Ø1, Ø2, Ø3 and Ø4 enter the ON state.
The current output from the transconductor 12, which is in proportion to the voltage of the input signal, is applied over the time length t to one of the capacitors, selected via the first switch 14, is integrated at the capacitor over the time length t, and is stored as an electrical charge. Then, the charge stored at the selected capacitor is output to the circuit at the rear stage for sampling. For instance, as the first switch 14 is controlled with the clock signal Ø1 and the first capacitor 20a is charged with the current output from the transconductor 12, the third switch 18 is controlled with the clock signal Ø2 to output the stored electrical charge to the circuit at the rear stage. Subsequently, the second switch is controlled with the clock signal Ø4 to ground the first capacitor 20a and, as a result, the residual charge is released and the first capacitor becomes initialized.
The capacitors 20a, 20b, 20c and 20d are each repeatedly engaged in sampling operations over time intervals t in response to the operations of the first switch 14, the second switch 16 and the third switch 18. Thus, the input signal is sampled with a rectangular time window t and since a notch occurs at a position corresponding to an integral multiple of 1/t due to the frequency characteristics, the charge domain filter circuit 10 is able to function as a SINC filter. For instance, assuming that t=1 ns, a notch occurs at 1 GHz (i.e., at a position corresponding to an integral multiple of 1/t) and the charge domain filter circuit 10 is able to function as a SINC filter achieving frequency characteristics such as those shown in FIG. 19.
(Nonpatent Reference Literature 1) L. Richard Carley and Tamal Mukherjee, “High-Speed Low-Power Integrating CMOS Sample-and-Hold Amplifier Architecture,” Proceedings of IEEE 1995 Custom Integrated Circuits Conference, pp 543˜546, May 1995
(Nonpatent Reference Literature 2) J. Yuan, “A Charge Sampling Mixer With Embedded Filter Function for Wireless Applications” proceedings of IEEE 2000 International Conference on Microwave and Millimeter Wave Technology, pp 315˜318, September 2000
(Nonpatent Reference Literature 3) A. Mirzaie, R. Bagheri, S. Cherazi and A. A. Abidi “A Second-Order Antialiasing Prefilter for an SDR Receiver”, Proceedings of IEEE 2005 Custom Integrated Circuits Conference, pp 629˜632, September 2005